Ahead of what will be a packed Intel Developer Forum, Sept. 22-24 in San Francisco, here’s some news around a newly planned family of future “embedded” processors for non-PC equipment and gear code-named Jasper Forest — and details around our manufacturing prowess, specifically in our shift to 32 nanometer production.
How do these relate? Well, while Jasper Forest will be based on 45 nanometer manufacturing, it takes advantage of that process and
our high-k, metal gate transistor technology to deliver eye-opening low-watt numbers. This manufacturing prowess also enables Jasper Forest to innovate and integrate, in this case adding in for the first time an I/O hub right into the chip. And of course, all of this just gets better as we prepare for our 32 nanometer process on tap. Both firsts for Intel.
(Note – a 32 nanometer, future Core processor video coming soon)
The News, Part I
Jasper Forest for embedded, communications and storage equipment will provide the same robust performance of our Nehalem-based Intel® Xeon® processor 5500 series – but with a 27-watt system power savings.
It’s another example of Intel innovating and integrating. For the first time, Intel will integrate the I/O hub directly onto a dual-processing Intel Xeon processor, eliminating the need for a separate I/O hub in the board design, thus providing “real estate” and power savings.
These design features and thermals will be ideal for dense storage and communications solutions such as Storage Bridge Bay designs and CompactPCI blades used in carrier equipment. The chips will also be used in wireless infrastructure, routers, military, security, IPTV, VoIP, NAS, SAN and wireless radio network controllers.
Another key benefit is the ability of developers to now use Intel architecture to run workloads that traditionally only functioned on non-Intel processors. For example, comms solutions can now consolidate workloads for both the control and data plane all on one Intel® architecture system.
Intel will highlight some companies who plan to integrate Jasper Forest at his IDF keynote speech next week.
The News, Part II
Intel’s process technology is by far the most advanced of any semiconductor manufacturer in the world. That and Moore’s Law help us to “innovate and integrate” to deliver those super-thin laptops with great battery life everyone loves, super-fast servers and desktop PC gaming dream machines, and much more.
Intel’s 32nm CPU process is now certified and Westmere CPU wafers are moving through the factory in support of planned Q4 revenue production.
Intel is now advancing to the second-generation high-k+ metal gate transistor formula, giving Intel a 3+ year advantage in addressing leaky and energy IN-efficient transistors. Intel has shipped >200 million 45nm CPUs using high-k+ metal gate transistors.
For the first time, Intel has developed a full-featured SoC process technology to complement the CPU-specific technology. This version is for our smarter System on Chip (SoC) product efforts, which emphasize lower power transistors.
These advances combine to deliver record performance in terms of the highest drive current (electricity that flows when a transistor is on); the lowest leakage currents (keeping a lid on wasteful or lost electricity) and the tightest gate pitch (how closely transistors can be pack in) versus any reported 32nm or 28nm technology in the industry.
In addition, our NMOS transistors now have 19% performance improvement over their 45nm counterparts and our PMOS transistors now have a 28% performance improvement over their 45nm counterparts.
Translation? Faster, more energy-efficient and sleeker computers and consumer devices, at lower costs.
Net-net, when you have hundreds of millions of transistors inside our chips like we do, all of this is critically important and advantageous.
Here is even more info on
both of these news announcements. And, please follow us at IDF…the
blog, on
twitter, our
fan page, and
media center.
The post Intel News Ahead of IDF: New Chips; Manufacturing Efforts appeared first on Technology@Intel.
